What is DisplayPort?

DisplayPort was designed to replace VGA, DVI, and FPD-Link by VESA . DisplayPort is backwards compatible with VGA, DVI and HDMI through the use of passive and active adapters.DisplayPort is the first display interface that relyson packetized data transmission, a form of digital communication found in technologies including Ethernet, USB, and PCI Express. It allows both internal and external display connections and, unlike legacy standards where differential pairs are fixed to transmitting a clock signal with each output, the DisplayPort protocol is based on small data packets known as micro packets, which can embed the clock signal in the data stream, allowing higher resolutions with fewer pins. Data packets also allows DisplayPort to extend, meaning additional features can be added over time without significant changes to the physical interface itself.

DisplayPort can be used to transmit audio and video simultaneously, and each one is optional and can be transmitted without the other. The video signal path can have six to sixteen bits per color channel, and the audio path can reacheight channels of 24-bit 192 kHz uncompressed PCM audio and can also encapsulate compressed audio formats in the audio stream. A bi-directional, half-duplex auxiliary channel carries device management and device control data for the Main Link, such as VESA EDID, MCCS, and DPMS standards. In addition, the interface is capable of carrying bi-directional USB signals.

Dual-mode DisplayPorts are designed to transmit a single-link DVI or HDMI 1.2/1.4 TMDS protocol across the interface through the use of an external passive adapter that selects the desired signal and converts it from 3.3 volts to 5 volts. Analog VGA and dual-link DVI require powered active adapters to convert the protocol and signal levels and do not rely on Dual-Mode. VGA adapters are powered by the DisplayPort connector, while dual-link DVI adapters may rely on an external power source (see Dual-mode).

The DisplayPort connector can have one, two, or four differential data pairs (lanes) in a Main Link, each with a raw bit rate of 1.62, 2.7, 5.4, or 8.1 Gbit/s per lane with self-clock running at 162, 270, 540, or 810 MHz. The effective data rates after decoding are 1.296, 2.16, 4.32, or 6.48 Gbit/s per lane (or 80% of the total), since data is 8b/10b encoded so each eight bits of information are encoded with a ten-bit symbol.
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